IMPLEMENTASI TAPIS DIGITAL FINITE IMPULSE RESPONSE (FIR) BERBASIS FPGA (FIELD PROGRAMMABLE GATE ARRAYS)

Dermawan, Denny (2012) IMPLEMENTASI TAPIS DIGITAL FINITE IMPULSE RESPONSE (FIR) BERBASIS FPGA (FIELD PROGRAMMABLE GATE ARRAYS). Seminar Nasional Komputer dan elektro (SENAPUTRO) 2012. pp. 79-83. ISSN 978-602-19997-1-4

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Abstract

Digital filter that was designed and implemented is a finite impulse response (FIR) low pass digital filter with hamming windowing method. This research steps : design finite impulse response low pass analog filter, design finite impulse response low pass digital filter, digital filter simulation and downloading the result from simulation to the XILINX SPARTAN II FPGA. Implementation of digital filter coefficient is based on bit pair recoding algorithm because this algorithm have a shortest delay time according to the other algorithms ( booth and paper & Pencil ) Simulation tool used in this research is ModelSim Xilinx Edition II ver 5.7c starter edition (MXE II v5.7c). The result of simulation is downloaded to the SPARTAN II FPGA that mounting on the XSA-100 Board from XESS Corp. Observation is done for various amplitude of input signal and analysis is done for : delay time, CLB used and error prosentation due to rounding in the implementation of digital filter coefficient.

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